The present invention related generally to differential attenuators and more specifically to a high speed differential attenuator formed on a low temperature co-fired ceramic substrate having a dual use buried layer.
Various type of dielectric materials are used for forming substrates for electronic applications. One common substrate material used for hybrid electronic circuits is an alumina ceramic material having conventional thick or thin film resistors and metallization formed on the top surface of the substrate. Alumina ceramic substrates have the advantage of being thermally conductive, which aids in the dissipation of heat generated by integrated circuit devices mounted on the substrate.
A typical high speed differential attenuator circuit used in differential probes, oscilloscope inputs or the like, has first and second closely positioned parallel resistor-capacitor divider networks. Each divider network has an input coupled to receive one of the differential input signals from a device under test and a center tapped output coupled to a differential buffer amplifier. The other end of each network is coupled to electrical ground. It is desirable to construct the entire attenuator circuit from a monolithic substrate, with integrated, laser-trimmable capacitors and resistors. This reduces circuit size and improves side to side matching of the attenuator pair. To maintain high bandwidth and small size, the active differential input buffer integrated circuit (IC) is attached to the substrate directly adjacent to the attenuator, and electrically connected to the attenuator with wire bonds or other means. For probes and similar circuits, the substrate is usually completely or partially inside (or near) a metal tube or some other type of electrical shield.
The use of alumina ceramic substrates has a number of drawbacks when used to build high speed differential attenuators. The alumina ceramic substrate is typically a relatively thick piece of material, with conventional thick or thin film resistors and metallization, and no interior layers. The trimmable shunt capacitor is formed using the entire substrate as a dielectric layer which must be fairly thick for structural reasons. Because of capacitive fringing, the trim range of such a capacitor is small in comparison to its total capacitance. This causes designs to have more capacitance than desired, or less trim range than needed for good yield. It is difficult to design an input capacitor using the entire substrate as a dielectric because of the sensitivity of the capacitor to assembly variations which makes it difficult to match the capacitors in each attenuator leg. Even if this can be done, the ratio of the series to shunt capacitance is still affected by changes in substrate thickness and dielectric constant due to fringing. In a more typical case, the input capacitor is formed by other means, such as an add-on surface mounted component or using another layer (such as thick film cross-over dielectric). In this case, there is no inherent tracking of the capacitor ratios.
Another drawback to using alumina ceramic substrates for differential attenuators is the degrading of the attenuators"" common mode rejection ratio (CMRR). Because of the large size and high capacitive fringing of attenuators mounted on alumina ceramic substrates, AC CMRR is degraded by even slight changes in the position of the substrate relative to the outside tube, input pins, or other mechanical structures. Also, capacitive coupling between the positive and negative sides of the differential attenuator, or between capacitors and relatively large, high value resistors that are necessary for high DC input impedance, can cause a xe2x80x9chookyxe2x80x9d frequency response which degrades both the differential response and the CMRR. This xe2x80x9chookyxe2x80x9d behavior cannot be compensated with standard trimmable capacitors or resistors, and places inherent limits on the CMRR.
Low temperature co-fired ceramic (LTCC) material is also used for forming dielectric substrates for electronic applications. The advantage of LTCC material is the ability for form buried components, such as resistors, capacitors, inductors, transformers and the like within the substrate. U.S. Pat. No. 5,604,673 teaches a low temperature co-fired ceramic substrate for power converters. The low temperature co-fired ceramic substrate includes a number of layers with various metallized conductors located on the outer surface and various inner layers of the substrate. A cavity into which an integrated circuit is placed may be formed with or without thermal vias being formed in the substrate immediately beneath the cavity. A heat sink is positioned underneath the substrate that mates with the thermal vias to provide thermal management for the electronic circuit formed on the substrate. Alternatively, the integrated circuit device may be positioned on the top surface of the substrate with thermal vias formed beneath the integrated circuit location. A cavity is formed in the substrate from the opposite side of the substrate that receives a heat sink. The heat sink mates with the thermal vias underneath the integrated circuit device for thermal management. A further alternative is to form an in-situ heat sink in the low temperature co-fired ceramic substrate using high thermal conductivity LTCC tape disposed in a hole formed in the substrate as described in U.S. Pat. No. 5,386,339.
Various strip line components and passive devices are formed in the low temperature co-fired ceramic substrate as required by the particular circuit design. For example, a capacitor may be formed by locating two parallel conductive plate structures adjacent to each other and separated by a low temperature co-fired ceramic layer in between. Conductive vias may be used to connect the plates to components on the surface of the substrate on other buried components in the substrate.
A drawback to the above described co-fired ceramic structures is providing the proper voltages to the integrated circuit device while providing thermal management of heat generated by the device. Generally, surface mounted IC devices have their bottom surface acting as a voltage input lead. The prior art teaches coupling this lead to a ground potential through the heat sink and vias. However, in high speed differential attenuator applications for differential input probes the voltage input lead on the bottom of the differential buffer amplifier is set at some voltage level, such as a negative source voltage while the heat sink needs to be set at ground potential. Coupling the heat sink to the voltage potential on the bottom of the integrated circuit device will place the voltage potential on the surface of the probe.
What is needed is a high speed differential attenuator design using a dielectric substrate that reduces the capacitive fringing to improve the trim range of the capacitors in the attenuator and improves the differential response and common mode rejection ratio. The attenuator design should reduce the sensitivity of the attenuator to variations in the substrate thickness and dielectric constant and positioning of the substrate in relation to electrical shield or other mechanical structures. Further, there is a need for an attenuator design using a LTCC substrate structure that allow the bottom surface voltage input leads of an differential buffer amplifier to be coupled to a non-electrical ground voltage supply while providing thermal management of the heat generated by the IC device. Such a design should have a minimal effect on the overall size of the substrate. The attenuator design should also provide flexibility in laying out and connecting various components formed on and in the substrate structure. Further, there is a need to combine elements of the thermal management structure with the component structures for maintaining a minimum size for the substrate.
Accordingly, the present invention is to a high speed differential attenuator formed on a low temperature co-fired ceramic substrate having first and second dielectric layers with each dielectric layer having top and bottom surfaces. The top surface of the first dielectric layer has a voltage potential lead formed thereon for receiving an integrated circuit device where the bottom surface of the integrated circuit device is a voltage input lead for the integrated circuit device. First and second parallel resistor-capacitor divider networks are formed as part of the substrate with each divider network having first and second parallel resistors and capacitors. Each divider network has an input node and a center tapped output node with each input node coupled to receive an input signal and each output node coupled to an input of the integrated circuit device. Each divider network further has first and second conductive elements formed on the top surface of the first dielectric layer functioning as first capacitive plates for the first and second capacitors. A third conductive element is disposed between the first and second dielectric layers and positioned beneath the first conductive element of each divider network functioning as the other capacitive plate for the first capacitor. The first and second conductive elements are electrically coupled together by an electrical conductor or as a single plate element. A fourth conductive element is disposed between the first and second dielectric layers and positioned beneath both of the second conductive elements of the divider networks and the voltage potential lead and functions as the other capacitive plates for the second capacitors of the divider networks and as a heat transfer layer. First and second electrically conductive vias are respectively coupled to the input nodes of the divider networks and to the respective third conductive elements. At least a first thermally conductive via is formed between the top and bottom surfaces of the second dielectric layer below the voltage potential lead and thermally coupled to the fourth conductive element disposed between the dielectric layers.
In the preferred embodiment of the invention, the high speed differential attenuator has a plurality of thermally conductive vias formed beneath the voltage potential lead in an array pattern. A heat sink may be disposed adjacent to the bottom surface of the second dielectric layer and thermally coupled to the thermally conductive via or vias. In the preferred embodiment of the invention, a conductive pattern is formed on the bottom surface of the second dielectric layer that is thermally coupled to the thermally conductive via or vias. The heat sink is disposed adjacent to the bottom surface of the second dielectric layer and thermally coupled to the third conductive pattern. The thermally conductive via or vias are preferably cylindrically formed bores filled with a high thermally conductive material, such as gold. It is also preferred that the thermally conductive via or vias be electrically conductive.
The respective divider networks have resistors formed on the top surface of the first dielectric layer using traditional thick or thin film processes. The fourth conductive element disposed between the dielectric layers is coupled to a ground potential and provides a ground node for each of the divider networks. The voltage potential lead is coupled to a negative voltage potential.
The first dielectric layer preferably has a thickness in the range of 0.004 inches and the second dielectric layer has a thickness in the range of 0.025 inches. The conductive patterns have a thickness in the range of 0.0005 inches. Each of the thermally conductive vias in the array have a bore diameter in the range of 0.010 inches and a center to center spacing in the range of 0.020 inches.
The objects, advantages and novel features of the present invention are apparent from the following detailed description when read in conjunction with appended claims and attached drawings.